Build Sequential Circuit
技能 已验证 活跃Build sequential (stateful) logic circuits including latches, flip-flops, registers, counters, and finite state machines. Covers SR latch, D and JK flip-flops, binary/BCD/ring counters, and Mealy/Moore FSM design with clock signal and timing analysis. Use when a circuit must remember past inputs, count events, or implement a state-dependent control sequence.
To provide a structured, expert-level procedure for designing and verifying complex sequential logic circuits, enabling users to build stateful digital systems.
功能
- Build sequential logic circuits
- Design latches, flip-flops, registers, counters, FSMs
- State diagram and transition table generation
- Excitation and output equation derivation
- Gate-level implementation guidance
- Timing analysis and verification
使用场景
- When a circuit must remember past inputs or maintain internal state
- Designing counters, shift registers, or sequence detectors
- Implementing finite state machines (Mealy or Moore)
- Adding clocked storage elements to digital datapaths
非目标
- Designing purely combinational logic circuits
- Physical layout and routing of circuit board components
- Simulation of analog circuit behavior
工作流
- Identify Memory and State Requirements
- Construct State Diagram and Transition Table
- Derive Excitation Equations
- Implement at Gate Level
- Verify via Timing Diagram and State Sequence Simulation
实践
- Digital logic design
- State machine design
- Circuit verification
- Formal methods
先决条件
- Behavioral specification (state diagram, table, regex, or description)
- Clock characteristics (edge/level, single/multi-phase)
- Optional: Flip-flop type preference
- Optional: Reset type preference
Practical Utility
- info:Usage examplesWhile the SKILL.md provides a detailed procedure and expected outputs, explicit end-to-end invocation examples with claimed outputs are missing, though implied by the procedure's completeness.
安装
/plugin install agent-almanac@pjt222-agent-almanac质量评分
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