Evaluate Boolean Expression
技能 已验证 活跃Evaluate and simplify Boolean expressions using truth tables, algebraic laws (De Morgan, distributive, absorption, idempotent, consensus), and Karnaugh maps for up to six variables. Use when you need to reduce a Boolean expression to its minimal sum-of-products or product-of-sums form, verify logical equivalence between two expressions, or prepare a minimized function for gate-level implementation.
To provide a structured and reliable method for reducing complex Boolean expressions to their simplest form, aiding in logic design and verification.
功能
- Simplifies Boolean expressions using truth tables
- Applies algebraic laws for minimization
- Utilizes Karnaugh maps for up to six variables
- Verifies logical equivalence between expressions
- Supports sum-of-products and product-of-sums forms
使用场景
- Reducing Boolean expressions for gate-level implementation
- Verifying logical equivalence of two expressions
- Preparing minimized functions for circuit design
- Teaching or reviewing Boolean algebra concepts
非目标
- Minimizing expressions with more than six variables using K-maps (will use Quine-McCluskey)
- Handling expressions with unsupported operators or syntax
- Performing circuit synthesis beyond the minimized expression output
安装
/plugin install agent-almanac@pjt222-agent-almanac质量评分
已验证类似扩展
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100Design and simulate a minimal CPU from scratch: define an instruction set architecture (ISA), build the datapath (ALU, register file, program counter, memory interface), design the control unit (hardwired or microprogrammed), implement the fetch-decode-execute cycle, and verify by tracing a small program clock cycle by clock cycle. The capstone "computer inside a computer" exercise that composes combinational and sequential building blocks into a complete processor.
Build Sequential Circuit
97Build sequential (stateful) logic circuits including latches, flip-flops, registers, counters, and finite state machines. Covers SR latch, D and JK flip-flops, binary/BCD/ring counters, and Mealy/Moore FSM design with clock signal and timing analysis. Use when a circuit must remember past inputs, count events, or implement a state-dependent control sequence.
Design Logic Circuit
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